1. Field of the Invention
The present invention relates to parallel analog-to-digital converters and, more particularly, to a converter with p=2.sup.r -1 comparators, where r is the number of binary digits of the converter output signal diminished by 1, wherein the analog signal is applied to the comparator inputs of one kind, wherein the inputs of the other kind are connected consecutively to the taps of a resistive voltage divider consisting of equal-value resistors and having a reference voltage Ur applied thereto, and wherein the analog signal is shifted by .DELTA.U=Ur/2.sup.r+1 for the duration of every second clock period of the converter sampling signal.
2. Description of the Prior Art
A parallel analog-to-digital converter of this kind is disclosed in prior European application No. 81102603.8, which claims the priority of German Patent Application P 30 15 141.8, and corresponds to U.S. patent application Ser. No. 237,187, now U.S. Pat. No. 4,352,123 filed Feb. 23, 1981 as one of two possibilities of reducing the number of comparators and resistors of the voltage divider connected to the reference voltage. The prior application describes in detail how the voltage change .DELTA.U is achieved by suitably wiring the voltage divider, while the implementation of the switchover of the comparator inputs fed with the analog signal is not covered.